Various electronic devices implement hardware logic that is driven by one or more clocks. Problems may arise which cause the clock(s) to fail. To protect against such failure, many computer systems implement multiple clock signal sources (e.g., oscillators) in a “failover” configuration. In such a configuration, if a primary oscillator fails, a backup oscillator takes over the tasks of the primary oscillator. However, the oscillators are likely to be out of phase with each other. As a result, failing over from the primary oscillator to the backup oscillator may introduce signal glitches, runt pulses, etc. into the clock signal, thereby negatively affecting the overall performance of the electronic device within which the clock is implemented.